Field of the Invention
The present invention relates to a comparison circuit which compares the magnitudes of voltages with high accuracy, and to a sensor device equipped with the same.
Background Art
In a general electronic circuit, a comparison circuit has been used as a circuit which compares a plurality of voltages and determines the magnitudes thereof (refer to, for example, Patent Document 1).
A circuit diagram of one example of a related art comparison circuit is illustrated in FIG. 7. The related art comparison circuit determines using a comparator whether the voltage of a difference between two input voltages is larger or smaller than a prescribed voltage. A problem arises in that in the above comparison, an offset voltage (input offset voltage) that the comparator has, and noise become error factors, thereby deteriorating accuracy. The above input offset voltage is generated due to a fluctuation in the characteristics of an element which configures an input circuit of the comparator by way of example. Further, the above noise is generated by flicker noise that a single transistor configuring a circuit has, and thermal noise that a single transistor or a resistive element has.
In order to reduce the influence of the offset voltage that the above-described comparator has, the comparison circuit illustrated in FIG. 7 is configured as follows. The comparison circuit has a comparator 15, a switch S13 connected between an inversion input terminal N13 of the comparator 15 and an output terminal thereof, a capacitor 13 connected between the inversion input terminal N13 of the comparator 15 and an input terminal N11, a switch S14 connected between a non-inversion input terminal N14 of the comparator 15 and a comparison voltage input terminal Nref10, a switch S11 connected between the non-inversion input terminal N14 of the comparator 15 and a connecting point N141, a capacitor 14 connected between an input terminal N12 and the connecting point N141, and a switch S12 connected between the connecting point N141 and a comparison voltage input terminal N10. Here, the voltage of the comparison voltage input terminal N10 is assumed to be V0, the voltage of the comparison voltage input terminal Nref10 is assumed to be Vref, the voltage of the input terminal N11 is assumed to be V1, the voltage of the input terminal N12 is assumed to be V2, the voltage of the inversion input terminal N13 of the comparator 15 is assumed to be VN, the voltage of the non-inversion input terminal N14 of the comparator 15 is assumed to be V4, and the voltage of the output terminal of the comparator 15 is assumed to be Vo. Further, the input offset voltage of the comparator 15 is assumed to be Voa.
The comparison circuit of FIG. 7 is operated under control of the switches S11 to S14 as illustrated in FIG. 8. One cycle of operation thereof is comprised of a sample phase φ1 and a comparison phase φ2. In the sample phase φ1, the switch S11 is turned OFF, and the switches S12 to S14 are turned ON. In the comparison phase φ2, the switch S11 is turned ON, and the switches S12 to S14 are turned OFF. φ1 or φ2 at the ends of the voltages of the connecting points and the terminals are respectively assumed to indicate the voltages in the sample phase φ1 or the comparison phase φ2.
In the sample phase φ1, the switch S11 is turned OFF and the switch S12 is turned ON to charge ΔVC4φ1=V0−V2φ1 into the capacitor 14. Since the switch S14 is ON, V4φ1=Vref is reached. Since the comparator 15 is operated as a voltage follower circuit because the switch S13 is ON, and has the input offset voltage Voa, Voφ1=V4φ1+Voa is reached. Further, since the switch S13 is ON, VNφ1=Voφ1 is reached, i.e., VNφ1=Vref+Voa is reached, so that ΔVC3φ1=VNφ1−V1φ1=Vref+Voa V1φ1 is charged into the capacitor 13. Collecting the electric charges accumulated in the capacitors 13 and 14 yields the following:ΔVC3φ1=Vref+Voa−V1φ1  (A1) andΔVC4φ1=V0−V2φ1  (A2)
In the comparison phase φ2, the switches S12 to S14 are turned OFF, and the switch S11 is turned ON. Since ΔVC3φ1 expressed in the equation (A1) is held in the capacitor 13, the voltage VN is as follows:VNφ2=V1φ2+ΔVC3φ1  (A3)
On the other hand, since ΔVC4φ1 expressed in the equation (A2) is held in the capacitor 14, the voltage V4 is as follows:V4φ2=V2φ2+ΔVC4φ1  (A4)
Eventually, the voltage VN expressed in the equation (A3) and the voltage V4 expressed in the equation (A4) are compared with each other in the comparator 15, and a high level or a low level is outputted from the output terminal.
Taking the input offset voltage Voa of the comparator 15 into consideration, the voltages to be compared by the comparator 15 are as follows:(V4φ2+Voa)−VNφ2={(V2φ2−V1φ2)−(V2φ1−V1φ1)}−(Vref−V0)  (A5)
The input offset voltage Voa of the comparator 15 is not included in the equation (A5). This shows that the input offset voltage of the comparator 15 is cancelled. Thus, the input voltage component {(V2φ2−V1φ2)−(V2φ1−V1φ1)} and the reference voltage component (Vref−V0) are compared by the comparator 15 in the comparison phase φ2. From the above, it is possible to realize a comparison circuit which removes the influence of the offset voltage component of the comparator, which becomes an error factor, and provides a highly accurate output reduced in error.
[Patent Document 1] Japanese Patent Application Laid-Open No. 2008-236737